QUKU: A Coarse Grained Paradigm for FPGA
نویسندگان
چکیده
To fill the gap between increasing demand for reconfigurability and performance efficiency, coarse grain reconfigurable architectures are seen to be an emerging platform. The advantage lies in quick dynamic reconfiguration and power efficiency. Despite having these advantages they have failed to show their mark. This paper describes the QUKU architecture, which uses a coarsegrained dynamically reconfigurable PE array overlaid on an FPGA. The lowspeed reconfigurability of the FPGA is used to optimize the CGRA for different applications, whilst the high-speed CGRA reconfiguration is used within an application for operator re-use.
منابع مشابه
QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection
To fill the gap between increasing demand for reconfigurability and performance efficiency, CGRAs are seen to be an emerging platform. In this paper, a new architecture, QUKU, is described which uses a coarse-grained reconfigurable PE array (CGRA) overlaid on an FPGA. The low-speed reconfigurability of the FPGA is used to optimize the CGRA for different applications, whilst the high-speed CGRA ...
متن کاملResource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays
FPGA vendors have recently started focusing on OpenCL for FPGAs because of its ability to leverage the parallelism inherent to heterogeneous computing platforms. OpenCL allows programs running on a host computer to launch accelerator kernels which can be compiled at run-time for a specific architecture, thus enabling portability. However, the prohibitive compilation times (specifically the FPGA...
متن کاملDesign and Implementation of an Efficient Programmable Floating Point Unit with Coarse - Grained FPGA Arun
The novel method is to optimize coarse-grained floating point units (FPUs) in a hybrid FPGA by employing common sub graph extraction to determine the number of floating point adders / subtracters (FAs), multipliers (FMs) and word blocks (WBs) in the FPUs. Single precision FP adders / subtracters (FAs) and FP multipliers (FMs), with normalization are generated using standard cell library design ...
متن کاملOutput Serialization for FPGA-based and Coarse-grained Processor Arrays
This paper deals with the mapping of loop programs onto processor arrays either implemented in an FPGA or available as (reconfigurable) coarse-grained processor architectures. Usually the proportion of processing elements to I/O-interfaces is much higher whereby problems of data transportation and synchronization are arising. In this realm, we propose a systematic approach in order to feed-out ...
متن کاملPixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications
Coarse-Grained Reconfigurable Arrays (CGRAs) enable ease of programmability and result in low development costs. They enable the ease of use specifically in reconfigurable computing applications. The smaller cost of compilation and reduced reconfiguration overhead enables them to become attractive platforms for accelerating high-performance computing applications such as image processing. The C...
متن کامل